Upgrades to the Large Hadron Collider (LHC) at CERN will increase its luminosity by a factor of 10, providing a higher rate of collisions, and correspondingly more data for the experiments. This allows physicists to study known particles such as the Higgs boson in greater detail, as well as search for new and rare phenomena. This High-Luminosity LHC (HL-LHC) is expected to produce at least 15 million Higgs bosons per year, compared with the three million measured in 2017.
Higher luminosity requires the experiments to operate at further elevated beam intensities and particle collision rates, making it necessary to upgrade the detectors and electronics at the heart of the experiments. Consequently, the CMS Binary Chip (CBC) was designed and developed as a replacement for the APV25 ASIC used in the original Silicon Tracker of the CMS experiment.
Designed in a 130nm CMOS technology, the CBC is a 254-channel readout ASIC with each channel comprised of a pre-amplifier, shaper, and a comparator that converts the analogue signals into binary 1s and 0s.
A CBC ASIC
The binary data is stored in a 512-deep pipeline memory to accommodate trigger latencies of up to 12.8 microseconds, more than treble those of the original experiment. When triggered, the binary data from the pipeline is output as a serial packet at 320 Mb/s in order to satisfy an expected average trigger rate of 1MHz.
In an innovation to assist with the selection of the most interesting events, the CBC will instrument double-layer 2S-modules, containing two overlaid silicon microstrip sensors aligned in a parallel orientation. Logic on the CBC makes use of this double-layer configuration to identify the correlation between clusters of hit strips on both detector layers, thereby identifying potential high transverse-momentum tracks that can be utilised in the first-level trigger processing.
This work was carried out in collaboration with Imperial College London, with funding from STFC.
Full-size 2S module prototype with 10x10cm Si detectors (image courtesy of CERN)
Written by Mark Prydderch, group leader of the ASIC Design team.
