Quentin, project lead, with the radiation-hardened chips: CDS_ADC (top left), STAR (right) and COMET (bottom left)For most science applications, operating in the visible and ultra-violet wavelengths, space-based camera systems typically employ Charge Coupled Devices (CCD) as their sensor of choice.
The low noise, large full-well capacity, and high-resolution large pixel array formats available make CCDs a good choice for high dynamic range focal planes.
However, the high-voltage (typically 10V - 30V) biases and control clocks needed to operate them fall outside of the range compatible with standard CMOS integrated circuits (typically <5V), thereby requiring discrete-component electronics to provide these voltages and signals.
With requirements for low volume, low mass, low power, high reliability and sufficient tolerance to the effects of space radiation, this makes the design of space-qualified CCD readout electronics a significant challenge. Even just sourcing the necessary space-qualified components to realise these functions can frequently be an issue.
At the Technology Department, we have sought to solve these issues by designing a family of custom ASICs, starting in the early 2000s with a pair of 3.3V ASICs, one to read out and digitise the output signals from CCD sensors, called CDS_ADC, and the other a multi-channel Digital to Analogue Converter (DAC) to allow adjustment of high-voltage CCD biases via a system of discrete op-amps and transistors.
While these devices provided higher levels of integration, functionality and performance than previously possible, and were used successfully to instrument several space missions (STEREO, Solar Dynamics Observatory), they did not address the requirement to generate the high-voltage biases and clock signals. This was resolved by the subsequent development of two compact mixed-signal high-voltage ASICs called STAR and COMET, delivering a complete space-qualified chipset for building compact low-mass space-based camera systems.
CDS_ADC
The CDS_ADC is a video processing ASIC designed specifically for the readout of CCDs and consists of a preamplifier with Correlated Double Sampling (CDS) and a 16-bit pipelined ADC.
A key feature of the design is the incorporation of a differential preamplifier with a signal gain of x4 that eliminates the need for an external preamplifier and provides enhanced rejection of common-mode noise and ground-bounce.
The CDS is performed within the preamplifier circuit using switched capacitors. The resulting analogue voltage is fed to the first stage of the 16-bit pipelined ADC and the corresponding digital word is output from the ASIC several cycles later.
STAR
The STAR biasing and telemetry ASIC is designed to provide all the static voltage biases required by science-grade CCDs, replacing the earlier multi-channel DAC ASIC with discrete op-amps and transistors.
The ASIC provides 24 fully independent voltage outputs for static biases with a programmable voltage range of 0 – 32.736V and a load current of up to 20mA.
A short circuit protection system limits the output current magnitude to a maximum of 25mA and the outputs can drive resistive loads as low as 1kΩ and capacitive loads from 10pF to at least 10μF.
Thanks to the high level of integration offered by ASICs, STAR also includes a telemetry ADC to provide housekeeping data on system voltages. The on-chip telemetry system allows for monitoring of the 24 generated output voltages along with several external single-ended and differential voltages using an on-chip 12-bit ADC, the input of which includes an optional x4 gain stage.
Control and programming of STAR is achieved using a simple SPI interface, and all required voltage and current references are generated internally so no additional active circuitry is needed to operate the ASIC.
Most of the device operates from a 3.3V power supply while the output drivers operate from high-voltage supplies set according to the output range required, nominally +35V and -2V for the full 32.736V range.
COMET
The COMET clock buffer ASIC (also known as C2BA) generates six independent high-voltage CCD clock signals from low-voltage CMOS inputs.
Each clock channel includes a pair of voltage regulators to generate user-defined high and low voltage levels for the output clock waveform with a range of 0V to 16.368V.
The clock drivers are defined-current output stages with independently programmable pull-up and pull-down currents in the range of 400µA to 409.6mA, which generate linear clock edges into capacitor-only loads such as CCD clock inputs.
As with the STAR ASIC, required reference currents and voltages are generated from on-chip bandgap circuits, and control of the device is via an SPI serial interface.
An on-chip digital control system ensures the safe and simple operation of this multiple voltage domain ASIC by correctly sequencing the activation and deactivation of subsystems to prevent damage that could destroy the ASIC.
Further built-in circuitry provides power supply monitoring and under-voltage lock-out functions as well as the automatic shutdown of the device and discharging of clock nodes in the event of a power failure.
Much of the device operates from 3.3V supplies, with the regulators and drivers using high-voltage supplies with nominal values of 18V and -2V if the full voltage range of 16.368V is required.
Space-ready design
All ASICs making up the chipset have been designed specifically for the radiation environment of space, using established design methods to harden against Total Ionising Dose (TID) and Single Event Latch-up (SEL) effects, and critical logic circuits utilising Triple Module Redundancy (TMR) to protect against soft data errors.
The ASICs operate to specification across a temperature range of -40°C to +125°C and have been designed to be tolerant to TID levels of 100kRad.
When used together these ASICs replace most of the discrete circuitry typically required for space-based CCD camera systems.
This development work continues with design work on a replacement for the CDS_ADC that will operate at higher resolution and speed while lowering power and introducing new features such as multi-sampling, expected to be completed in 2025.
Quentin Morrissey, Project Lead, said:
"The CDS_ADC chip was created by our team, 20-plus years ago, in collaboration with RAL Space. They required space-qualified integrated electronics to enable them to continue to develop their space-based cameras for solar physics applications. The chip was a great success, and its capabilities and performance remain a unique selling point of RAL Space cameras.
"Since its development, the ASIC has been used in multiple NASA missions, including the Solar Dynamics Observatory (2010) and STEREO (2006). In fact, any high-resolution image of the surface of the sun, showing loops and whirls, likely comes from the Solar Dynamics Observatory and most of the detectors on the observatory use the CDS ADC.
"More recently, we have created two new ASICS, STAR and COMET, to complement the CDS_ADC and bringing the same benefits and principles to the design of the camera drive electronics. Integrating the high voltage circuits makes them smaller, more power efficient, and radiation hardened. This in turn makes the camera electronics lighter and cheaper. Both the development of new chips and use of existing ones is an ongoing and evolving line of work, with the latest version of the CDS_ADC being used on the NASA PUNCH mission."
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